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toshiba toshiba corporation 1/14 tlcs-90 series TMP90PH48 the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 8?it microcontrollers TMP90PH48f 1. outline and characteristics the tmp90pm48 is a system evalution lsi having a built in one-time prom for tmp90c848. a programming and veri?ation for the internal prom is achieved by using a general eprom programmer with an adapter socket. the function of this device is exactly same as the tmp90c848 by programming to the internal prom. the differences between TMP90PH48 and tmp90c848 are the memory size (rom). the following are the memory map of TMP90PH48 and tmp90c848. parts no. rom ram package adapter socket no. TMP90PH48n otp 16384 x 8bit 512 x 8bit 80-fp bm1153 www.datasheet.in
2/14 toshiba corporation TMP90PH48 figure 1. TMP90PH48f block diagram www.datasheet.in
toshiba corporation 3/14 TMP90PH48 2. pin assignment and functions the assignment of input/output pins, their names and func- tions are described below. 2.1 pin assignment figure 2.1 shows pin assignment of the TMP90PH48. figure 2.1 pin assignment (80-fp) www.datasheet.in
4/14 toshiba corporation TMP90PH48 2.2 pin names and functions the TMP90PH48 has mcu mode and prom mode. (1) mcu mode (the tmp90c848 and TMP90PH48 are pin compatible) table 2.2 (1/2) pin name no. of pins i/o or tristates function p00 ~ p07 8 i/o port 0: 8-bit i/o port. each bit can be set for input or output. p10 ~ p17 8 i/o port 1: an 8-bit i/o port.each bit can be set for input or output pull-up resistance included. p20 ~ p27 8 i/o port 2: 8-bit output port. p30 1 output port 30: 1-bit output port. p31 1 output port 31: 1-bit output port. p32 /txd 1 output port 32: 1-bit output port. output used to transmit serial data. p32 /rxd 1 input port 33: 1-bit output port. input used to receive serial data. p40 ~ p47 8 i/o port 4: 8-bit i/o port. each bit can be set for input or output (p40 - p43 o.d. 4ma sink, p44 - 47 10ma source). p50 ~ p57 /an0 ~ an7 8 input port 5: 8-bit input port. input analog input: 8-bit analog input to the a/d converter. p60 ~ 67 /an8 ~ an15 8 input port 6: 8-bit input port. input analog input: 8-bit analog input the a/d converter p70 ~ p73 4 i/o port 7: 4-bit i/o port. each bit can be set for input or output. programmable pull-up resistance included. p80 /t01 1 i/o port 80: 1-bit i/o port. output timer output 1: used for timer 0 or timer 1 output. p81 /t03 1 i/o port 81: 1-bit i/o port. output timer output 3: used for timer 2 or timer 3 output. p82 /int0 1 i/o port 82: 1-bit i/o port. input interrupt request pin 0: level/rising edge programmable interrupt request pin. p83 /int1 /ti4 1 i/o port 83: 1-bit i/o port. input interrupt request pin 1: rising/falling edge programmable interrupt request pin. input timer input 4: count input/capture trigger signal for timer 4. www.datasheet.in
toshiba corporation 5/14 TMP90PH48 table 2.2 (2/2) pin name no. of pins i/o or tristate function p84 /int2 /ti5 1 i/o port 84: 1-bit i/o port. input interrupt request pin 2: rising edge programmable interrupt request pin. input timer input 5: count input/capture trigger signal for timer 5. p85 /t04 1 i/o port 85: 1-bit i/o port. output timer output 4: used as the timer 4 output. ale 1 output address latch enable signal: the falling edge of this signal used as the timing to latch ad0 ~ ad7 addresses when accessing external memory. clk 1 output clock output: generates clock pulse at 1/4 frequency of clock oscillation. pulled up during resetting. ea 1 input external access: connected to the v cc pin when using the tmp90c848f with built-in rom. reset 1 input reset: initializes the tmp90c848f. x1/x2 2 i/o high-speed crystal oscillator connection pin. x1?x2 2 i/o low-speed crystal oscillator connection pin. test1/test2 2 i/o testing pins connects directly test1 and test2 at a normal state operation. avcc 1 comparator power supply for the a/d converter. vref 1 a/d converter reference voltage input. avss 1 analog gnd pin (0v) v cc 2 power supply (+5v 10%) v ss 3 gnd pin www.datasheet.in
6/14 toshiba corporation TMP90PH48 (2) prom mode pin function name no. of pins i/o function pin name (mcu mode) a7 ~ a0 8 input address inputs p27 ~ p20 a15 ~ a8 8 input p15 ~ p10 d7 ~ d0 8 i/0 data input/output p07 ~ p00 oe 1 input output enable input p30 ce 1 input chip enable signal input p31 vpp 1 power supply 12.5v/5v(programming power supply) ea vcc 1 power supply 5v vcc vss 1 power supply 0v vss pin names no. of pins i/o pin setting p16, p17 2 output be fixed to ??level (note). p32, p33 2 output, input be fixed to ??level. p40 ~ p47 8 i/o be fixed to ??level. p50 ~ p57 p60 ~ p67 8 8 input be fixed to ??level. p70 ~ p73 4 i/o be fixed to ??level. p80 ~ p85 6 i/o be fixed to ??level. vref/ avss/avcc 3 be fixed to ??level. reset 1 input refer to figure 3.2 clk 1 output x1 1 input resonator connection pin x2 1 output x1 1 input x2 1 output www.datasheet.in
toshiba corporation 7/14 TMP90PH48 3. operation the TMP90PH48 is the otp version of the tmp90cc848 that is replaced an internal rom from mask rom to eprom. the function of TMP90PH48 is exactly same as that of tmp90cc848 except the internal rom size. refer to the tmp90c848 except the functions which are not described this section. the following is an explanation of the hardware con?ura- tion and operation in relation to the tmp90ch48. the TMP90PH48 has an mcu mode and a prom mode. 3.1 mcu mode (1) mode setting and function the mcu mode is set by opening the clk pin (output status). in the mcu mode, the operation is same as that of tmp90c848. (2) memory map figure 3.1 shows the memory map TMP90PH48, and the accessing area by the respective addressing mode. figure 3.1. TMP90PH48f memory map www.datasheet.in
8/14 toshiba corporation TMP90PH48 3.2 prom mode (1) mode setting and function prom mode is set by setting the reset and clk pins to the ??level. the programming and veri?ation for the internal prom is achieved by using a general eprom pro- grammer with the adapter socket. the device slection (rom type) should be ?7256?with following conditions. size = 256kbit (32kx 8bit) tpw = 1ms, vpp = 12.5v) figure 3.2 shows the setting of pins in prom mode figure 3.2. prom mode pin setting (2) programming flow chart the programming mode is set by applying 12.5v (pro- gramming voltage) to the vpp pin when the following pins are set as follows, (vcc : 6.0v) *these conditions can be ( reset : ??level) obtained by using adaptor (clk : ??level) socket. after the address and data have been ?ed, a data on the data bus is programmed when the ce pin is set to ?ow?(1ms plus is required). general programming procedure of an eprom programmer is as follows, ?write a data to a speci?d address for 1ms. ?verify the data. if the read-out data does not match the expected data, another writing is performed until the correct data is written (max. 25 times). after the correct data is written, an additional writing is performed by using three times longer programming pulse width (1ms x programming times), or using three times more programming pulse number. then, verify the data and increment the address. the veri?ation for all data is done under the condition of vpp = vcc = 5v after all data were written. figure 3.3 shows the programming ?w chart. www.datasheet.in
toshiba corporation 9/14 TMP90PH48 figure 3.3. flow chart www.datasheet.in
10/14 toshiba corporation TMP90PH48 (3) the security bit the TMP90PH48 has the security bit in prom cell. if the security bit is programmed to ?? the content of the prom is disable to read in prom mode. how to program the security bit. 1) connect a15 pins to vcc. [otherwise connect them gnd to program prom, (address 0000h ~ 3fffh) 2) set programming address to 0000h. 3) to program the security bit, do to ? 4) set d2 ~ d7 to ?? respectively. table 3.1 data to program bit to program d0 ~ d7 a0 ~ a12 a15 the security bit feh all ? all ? prom (0000h ~ 1fffh) all ? www.datasheet.in
toshiba corporation 11/14 TMP90PH48 4. electrical characteristics TMP90PH48 4.1 absolute maximum ratings symbol item rating unit v cc power supply voltage -0.5 ~ + 7 v v in input voltage -0.5 ~ v cc + 0.5 v p d power dissipation (ta = 70 c) 500 mw t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -20 ~ 70 c 4.2 dc characteristics v cc = 5v 10% ta = ?0 ~ 70 c high-speed clock: 16 ~ 20mhz, low-speed clock: 0.5 ~ 1mhz typical values are for ta = 25 c and vcc = 5v symbol parameter min max unit condition v il input low voltage (p0) -0.3 0.8 v v il1 p1, p3, p4, p5, p6, p7, p8 -0.3 0.3v cc v v il2 reset , p82 (into) -0.3 0.25v cc v v il3 ea -0.3 0.3 v v il4 x1, x1 -0.3 0.2v cc v v ih input high voltage (p0) 2.2 v cc + 0.3 v v ih1 p1, p3, p4, p5, p6, p7, p8 0.7v cc v cc + 0.3 v v ih2 reset , p82 (into) 0.75v cc v cc + 0.3 v v ih3 ea v cc -0.3 v cc + 0.3 v v ih4 x1, x1 0.8v cc v cc + 0.3 v v ol v ol1 output low voltage (open drain sink) 0.45 0.45 v 0.45 i ol = 1.6ma i ol = 4ma v oh v oh1 v oh2 v oh3 output high voltage p44 ~ 47 (open drain source) 2.4 0.75v cc 0.9v cc 2.4 v v v 0.45 i oh = -400 m a i oh = -100 m a i oh = -20 m a i oh = 10 m a i li input leakage current 0.02 (typ) 5 m a 0.0 vin v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 vin v cc - 0.2 i cc (vcc - vss) operating current (run) idle 1 15 (typ) 1.5 (typ) 30 5 ma ma high-speed clock: 20mhz low-speed clock: 1mhz stop (ta = -20 ~ 7 c) stop (ta = 0 ~ 50 c) 0.2 (typ) 40 10 m a m a 0.2 vin v cc -0.2 alcc avcc - avss) operating current 7 (typ) 15 ma fosc = 10mhz avcc = 5v 10% v stop power down voltage (@stop) ram back up 2.0 6.0 v v il2 = 0.2v cc , v ih2 = 0.8v cc r rst reset , p1, p7, pull up register 30 130 k w cio pin capacitance 10 pf testfreq = 1mhz v th schmitt width (reset , p82) 0.4 1.0 (typ) v www.datasheet.in
12/14 toshiba corporation TMP90PH48 4.3 a/d converter characteristics v cc = 5v 10% ta = -20 ~ 70 c high-speed clock: 16 ~ 20mhz, low-speed clock: 0.5 ~ 1mhz symbol parameter condition min typ max unit v ref analog reference voltage 3.5 vcc vcc v d v ref analog reference voltage range v ref - vss 3.5 vcc vcc avss analog power supply voltage vss vss vss v ain analog input voltage range vss vcc i refad supply current for analog reference voltage 0.8 2 ma this a/d converter is guaranteed only monotonicity because it has an offset value (when vain = 0v), but the 8-bit resolution is gotten except an offset value. the a/d converted data is recommended to be processed relatively. figure 4.3 (1). a/d converter typical conversion characterics (v ref = 5v, vss = 0v) 4.4 zero-cross characteristics v cc = 5v 10% ta = -20 ~ 70 c high-speed clock: 16 ~ 20mhz, low-speed clock: 0.5 ~ 1mhz symbol item condition min max unit v zx zero-cross detection input for ac, c = 0.1 m f 1 1.8 vac p- p a zx zero-cross accuracy 50/60hz sine wave 135 mv f zx zero-cross detection input frequency 0.04 1 khz 4.5 timer/counter input clock (ti0, ti2, and ti4) v cc = 5v 10%ta = -20 ~ 70 c high-speed clock: 16 ~ 20mhz, low-speed clock: 0.5 ~ 1mhz symbol parameter variable 10mhz clock unit min max min max t vck clock cycle 8x + 100 900 ns t vckl low clock pulse width 4x + 40 440 ns t vckh high clock pulse width 4x + 40 440 ns www.datasheet.in
toshiba corporation 13/14 TMP90PH48 4.7 read operation (prom mode) tcyc = 400ns (10mhz clock) a = 200ns 4.8 programming operation (prom mode) 4.6 interrupt operation v cc = 5v 10%ta = -20 ~ 70 c high-speed clock: 16 ~ 20mhz, low-speed clock: 0.5 ~ 1mhz symbol item variable 10mhz clock unit min max min max t intal nmi , int0 low level pulse width 4x 400 ns t intah nmi , int0 high level pulse width 4x 400 ns t intbl int1, int2 low level pulse width 8x + 100 900 ns t intbh int1, int2 high level pulse width 8x + 100 900 ns dc characteristic, ac characteristic ta = -40 ~ 85 c vcc = 5v 10% symbol parameter condition min max unit v pp v ih1 v il1 v pp read voltage input high voltage (a0 ~ a15, ce , oe ) input low voltage (a ~ a15, ce , oe ) 4.5 0.7 x v cc -0.3 5.5 vcc + 0.3 0.3 x v cc v v v t acc address to output delay c l = 50 p f 2.25tcyc + a ns dc characteristic, ac characteristic ta = 25 5 c vcc = 6v 0.25v symbol parameter condition min typ max unit v pp v ih v il v ih1 v il1 i cc i pp programming voltage input high voltage (d0 ~ d7) input low voltage (d0 ~ d7) input high voltage (a0 ~ a15, ce , oe ) input low voltage (a0 ~ a15, ce , oe ) v cc supply current v pp supply current - - - - - t osc = 10mhz v pp = 13.00v 12.25 0.2v cc + 1.1 -0.3 0.7v cc -0.3 - - 12.50 12.75 v cc + 0.3 0.2v cc - 0.1 v cc + 0.3 0.3v cc 50 50 v v v v v ma ma t pw ce program pulse width c l = 50 p f 0.95 1.00 1.05 ms www.datasheet.in
14/14 toshiba corporation TMP90PH48 4.9 read operation timing chart (prom mode) 4.10 programming operation timing chart (prom mode) www.datasheet.in

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